ICLAB Lab06 Note

Week 7

CheckSum (CS)

First design a checksum soft IP which can calculate the checksum of the input data. Second design a processor which contains 2 checksum IPs.

This refers to DesignWare Library. Used when a design uses some DesignWare IPs for optimization purposes.

Specifies a list of libraries of cells used solely for reference.

In a design, inevitably we use some third party IPs, e.g. PLL, RAM, PAD. Using Link Library let DC know that it does not need to synthesize these parts but it can get information from the .lib files in Link Library.

Specifies the technology library whose standard cells the designers want DC to infer and finally map to.

During synthesis, DC selects gates from target library, and calculates the timing of the circuit based on the timing data of the .lib files provided by ASIC Vendor(UMC, TSMC, …).

The target library name should also be included in the Link Library.

DC will not be able to link to the mapped cells in the netlist, if the target library name is not included in the link library list.

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